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SP37E760
PRELIMINARY
3.3V I/O Controller for Embedded Applications
FEATURES
3.3 Volt Operation Intelligent Auto Power Management 16 Bit Address Qualification (Optional) Serial Ports - Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry ISA Host Interface General Purpose Address Decoder - 16-Byte Block Decode Multi-Mode Parallel Port with ChiProtect - Standard Mode - IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - Enhanced Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) - Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 7 IRQ and 3 DMA Options 100 Pin QFP and TQFP Packages
GENERAL DESCRIPTION
The SMSC SP37E760 is a 3.3v PC 97-compliant I/O Controller. The SP37E760 utilizes SMSC's proven SuperCell technology and is optimized for embedded applications. The SP37E760 incorporates a 16-byte data FIFO, two 16C550 compatible UARTs and one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support. Both on-chip UARTs are compatible with the NS16C550. The parallel port is compatible with IBM PC/AT architectures. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the SP37E760 is not powered. The SP37E760 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The SP37E760 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable system configuration of key functions such as the parallel port, and UARTs.
ORDERING INFORMATION
Order Numbers: SP37E760-MC for 100 Pin QFP Package SP37E760-MD for 100 Pin TQFP Package
SMSC DS - SP37E760
Rev. 04/13/2001
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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TABLE OF CONTENTS 1 2 2.1 2.2 2.3 3 3.1 4 PIN CONFIGURATIONS ....................................................................................................................... 6 PIN DESCRIPTION ............................................................................................................................... 8 BUFFER TYPE PER PIN...................................................................................................................... 8 BUFFER TYPE SUMMARY ................................................................................................................. 12 OUTPUT DRIVERS ........................................................................................................................... 12 FUNCTIONAL DESCRIPTION............................................................................................................ 14 HOST PROCESSOR INTERFACE ........................................................................................................ 14 SERIAL PORT (UART) ....................................................................................................................... 15
4.1 REGISTER DESCRIPTION ................................................................................................................. 15 4.1.1 RECEIVE BUFFER REGISTER (RB) ................................................................................... 15 4.1.2 TRANSMIT BUFFER REGISTER (TB) ................................................................................. 15 4.1.3 INTERRUPT ENABLE REGISTER (IER).............................................................................. 15 4.1.4 INTERRUPT IDENTIFICATION REGISTER (IIR) ................................................................ 16 4.1.5 FIFO CONTROL REGISTER (FCR) ..................................................................................... 17 4.1.6 LINE CONTROL REGISTER (LCR)...................................................................................... 18 4.1.7 MODEM CONTROL REGISTER (MCR)............................................................................... 19 4.1.8 LINE STATUS REGISTER (LSR) ......................................................................................... 20 4.1.9 MODEM STATUS REGISTER (MSR) .................................................................................. 21 4.1.10 SCRATCHPAD REGISTER (SCR) ....................................................................................... 21 4.1.11 PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES ................................ 21 4.1.12 The Affects of RESET on the UART Registers ..................................................................... 22 4.2 FIFO INTERRUPT MODE OPERATION................................................................................................ 23 4.3 FIFO POLLED MODE OPERATION .................................................................................................... 23 4.4 NOTES ON SERIAL PORT FIFO MODE OPERATION ........................................................................... 25 4.4.1 GENERAL ............................................................................................................................. 25 4.4.2 TX AND RX FIFO OPERATION............................................................................................ 25 5 PARALLEL PORT............................................................................................................................... 27 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES .............................................. 28 DATA PORT .......................................................................................................................... 28 STATUS PORT ..................................................................................................................... 28 CONTROL PORT.................................................................................................................. 29 EPP ADDRESS PORT.......................................................................................................... 29 EPP DATA PORT 0............................................................................................................... 29 EPP DATA PORT 1............................................................................................................... 29 EPP DATA PORT 2............................................................................................................... 30 EPP DATA PORT 3............................................................................................................... 30 EPP 1.9 OPERATION................................................................................................................... 30 Software Constraints ............................................................................................................. 30 EPP 1.9 Write ........................................................................................................................ 30 EPP 1.9 Read........................................................................................................................ 31 EPP 1.7 OPERATION................................................................................................................... 31 Software Constraints ............................................................................................................. 31 EPP 1.7 Write ........................................................................................................................ 31 EPP 1.7 Read........................................................................................................................ 32 EXTENDED CAPABILITIES PARALLEL PORT ........................................................................... 33 Vocabulary ............................................................................................................................ 33 ISA IMPLEMENTATION STANDARD................................................................................... 34 Description ............................................................................................................................ 34 Register Definitions ............................................................................................................... 35 OPERATION ......................................................................................................................... 39 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.2 5.2.1 5.2.2 5.2.3 5.3 5.3.1 5.3.2 5.3.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5
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AUTO POWER MANAGEMENT......................................................................................................... 43
6.1 PIN BEHAVIOR ................................................................................................................................ 43 6.1.1 System Interface Pins ........................................................................................................... 43 6.2 UART POWER MANAGEMENT.......................................................................................................... 43 6.3 PARALLEL PORT ............................................................................................................................. 44 7 CONFIGURATION .............................................................................................................................. 45 7.1 CONFIGURATION ACCESS PORTS..................................................................................................... 45 7.2 CONFIGURATION STATE................................................................................................................... 45 7.2.1 Entering the Configuration State ........................................................................................... 45 7.2.2 Configuration Register Programming.................................................................................... 45 7.2.3 Exiting the Configuration State.............................................................................................. 45 7.2.4 Programming Example.......................................................................................................... 46 7.2.5 Configuration Select Register (CSR) .................................................................................... 46 7.3 CONFIGURATION REGISTERS DESCRIPTION ...................................................................................... 46 7.3.1 CR00 ..................................................................................................................................... 48 7.3.2 CR01 ..................................................................................................................................... 48 7.3.3 CR02 ..................................................................................................................................... 49 7.3.4 CR03 ..................................................................................................................................... 49 7.3.5 CR04 ..................................................................................................................................... 50 7.3.6 CR05 ..................................................................................................................................... 50 7.3.7 CR06 ..................................................................................................................................... 50 7.3.8 CR07 ..................................................................................................................................... 51 7.3.9 CR08 ..................................................................................................................................... 51 7.3.10 CR09 ..................................................................................................................................... 51 7.3.11 CR0A ..................................................................................................................................... 52 7.3.12 CR0B ..................................................................................................................................... 52 7.3.13 CR0C..................................................................................................................................... 52 7.3.14 CR0D..................................................................................................................................... 53 7.3.15 CR0E ..................................................................................................................................... 53 7.3.16 CR0F ..................................................................................................................................... 53 7.3.17 CR10 ..................................................................................................................................... 53 7.3.18 CR11 ..................................................................................................................................... 53 7.3.19 CR12 - CR13......................................................................................................................... 54 7.3.20 CR14 ..................................................................................................................................... 54 7.3.21 CR15 ..................................................................................................................................... 54 7.3.22 CR16 ..................................................................................................................................... 54 7.3.23 CR17 ..................................................................................................................................... 54 7.3.24 CR18 - CR1D ........................................................................................................................ 54 7.3.25 CR1E ..................................................................................................................................... 55 7.3.26 CR1F ..................................................................................................................................... 55 7.3.27 CR20 ..................................................................................................................................... 55 7.3.28 CR21 - CR22......................................................................................................................... 55 7.3.29 CR23 ..................................................................................................................................... 55 7.3.30 CR24 ..................................................................................................................................... 55 7.3.31 CR25 ..................................................................................................................................... 55 7.3.32 CR26 ..................................................................................................................................... 56 7.3.33 CR27 ..................................................................................................................................... 56 7.3.34 CR28 ..................................................................................................................................... 56 7.3.35 CR29 ..................................................................................................................................... 57 7.3.36 CR2A ..................................................................................................................................... 57 7.3.37 CR2B ..................................................................................................................................... 57 7.3.38 CR2C..................................................................................................................................... 57 7.3.39 CR2D..................................................................................................................................... 58 7.3.40 CR2E ..................................................................................................................................... 58 7.3.41 CR2F ..................................................................................................................................... 58 8 OPERATIONAL DESCRIPTION ......................................................................................................... 59
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8.1 8.2 9
MAXIMUM GUARANTEED RATINGS ......................................................................................... 59 DC ELECTRICAL CHARACTERISTICS ...................................................................................... 59 AC TIMING .......................................................................................................................................... 62
9.1 HOST TIMING .................................................................................................................................. 62 9.2 SERIAL PORT TIMING ...................................................................................................................... 65 9.3 PARALLEL PORT TIMING .................................................................................................................. 66 9.3.1 Parallel Port EPP Timing....................................................................................................... 67 9.3.2 Parallel Port ECP Timing....................................................................................................... 71 10 11 PACKAGE OUTLINES .................................................................................................................... 76 SP37E760 REVISIONS ................................................................................................................... 78
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PIN CONFIGURATIONS
nDSR1 TXD1 RXD1 nSTROBE nAUTOFD nERROR nINIT nSLCTIN VCC PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 nACK BUSY PE SLCT PWRGD RESET D7 D6 D5 D4 DRQ_B 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nRTS1 nCTS1 nDTR1 nRI1 nDCD1 nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2 ADRX/IRQ_B VSS nDACK_C A10 IRQIN DRQ_C IOCHRDY 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 D2 D1 D0 VSS AEN nIOW nIOR A9 A8 A7 IRQ_F IRQ_E IRQ_D IRQ_C nDACK_B TC A6 A5 A4 A3
SP37E760 100 PIN QFP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC NC NC NC NC VSS NC NC NC NC NC VSS VSS VSS VCC VSS VSS NC IRQ_A CLK14 DRQ_A nDACK_A NC IRQ_H VSS NC nCS A0 A1 A2
FIGURE 1 - SP37E760 QFP PIN CONFIGURATION
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D3
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nSTROB E nAUTOF D nERRO nINR T nSLCTI VCN C PD 0 PD 1 PD PD 2 3 VSS PD 4 PD 5 PD 6 PD nAC 7 K BUS Y PE SLC T PWRG
75 74737271706968676665646362616059 5857565554 535251 RXD1 TXD1 nDSR1 nRTS1 nCTS1 nDTR1 nRI1 nDCD1 nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2 ADRX/IRQ_B VSS nDACK_C A10 IRQIN DRQ_C IOCHRDY NC NC 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 1011121314151617 1819202122 23 2425 DRQ_B D3 D2 D1 D0 VSS AEN nIOW nIOR A9 A8 A7 IRQ_F IRQ_E IRQ_D IRQ_C nDACK_B TC A6 A5 A4 A3 A2 A1 A0
SP37E760 100 PIN TQFP
NC NC NC NC NC VSS VSS VSS VC C VSS VSS
NC NC NC VSS
FIGURE 2 - SP37E760 TQFP PIN CONFIGURATION
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IRQ_ NC A CLK1 4 DRQ_ A nDACK_ A NC IRQ_ H VSS NC nC S
D RESE DT 7 D 6 D 5 D 4
Rev. 04/13/2001
2 2.1
PIN DESCRIPTION Buffer Type Per Pin
Table 1 - DESCRIPTION OF PIN FUNCTIONS PIN # BUFFER TYPE
TQFP 46-49 51-54
QFP 48-51 53-56 44 45 46
NAME
SYMBOL
DESCRIPTION
42 43 44
26-32 39-41, 95
28-34 41-43, 97 21,52, 99
19,50, 97
20,34, 94
22,36, 96 35
33
17, 35-38, 22
19, 37-40, 24
25 55
27 57
HOST PROCESSOR INTERFACE D0-D7 IO12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. nI/O Read nIOR IS This active low signal is issued by the host microprocessor to indicate an I/O read operation. nI/O Write nIOW IS This active low signal is issued by the host microprocessor to indicate an I/O write operation. Address AEN IS Active high Address Enable indicates DMA operations Enable on the host data bus. Used internally to qualify appropriate address decodes. Address Bus A0-A10 I These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A10 address bits. DMA Request DRQ_A O12 These active high outputs are the DMA request for byte transfers of data between the host and the chip. A, B, C DRQ_B These signals are cleared on the last byte of the data DRQ_C transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). nDMA nDACK_A IS These are active low inputs acknowledging the request for a DMA transfer of data between the host Acknowl-edge nDACK_B and the chip. These inputs enable the DMA read or A, B, C nDACK_C write internally. Terminal TC IS This signal indicates that DMA data transfer is Count complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. Interrupt IRQ_A O12/OD12 Interrupt requests from a logical device or IRQIN are Request output on one of the IRQA-H signals. Refer to the IRQ_C configuration registers section for additional A, C, D, IRQ_D information. E, F, and H IRQ_E If EPP or ECP Mode is enabled this output is pulsed IRQ_F low and released to allow sharing of interrupts. IRQ_H Chip Select nCS I This active low input serves as an external decoder Input for address lines above A10. Data Bus 0-7 This active high signal resets the chip and must be valid for 500ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. I/O Channel IOCHRDY OD12 This pin is pulled low to extend the read/write Ready (Note3) command. IOCHRDY can be used by the Parallel Port in EPP mode. SERIAL PORTS INTERFACE Receive Data RXD2 IS Receiver serial data input for port 2. 2 Reset RESET IS
98
100
86
88
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PIN # TQFP 87 QFP 89
NAME Transmit Data 2 (Note4) Receive Data 1 Transmit Data 1 nRequest to Send (System Option)
SYMBOL TXD2
BUFFER TYPE O12PD
DESCRIPTION Transmit serial data output for port 2.
76 77 79,89
78 79 81,91
RXD1 TXD1 nRTS1 nRTS2 (SYSOPT)
I O12 O6
Receiver serial data input for port 1. Transmit serial data output for port 1. Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. At the trailing edge of hardware reset the nRTS2 inputs is latched to determine the configuration base address: 0 = INDEX Base I/O Address 3F0 Hex; 1 = INDEX Base I/O Address 370 Hex. Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. Active low Data Set Ready inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. Active low Data Carrier Detect inputs for the serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD.
81,91
83,93
nData Terminal Ready
nDTR1 nDTR2
O6
80,90
82,92
nClear to Send
nCTS1 nCTS2
I
78,88
80,90
nData Set Ready
nDSR1 nDSR2
I
83,85
85,87
nData Carrier Detect
nDCD1 nDCD2
I
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PIN # TQFP 82,84 QFP 84,86
NAME nRing Indicator
SYMBOL nRI1
BUFFER TYPE I (Note1)
DESCRIPTION
71
73
nPrinter Select Input 2 (Note )
Active low Ring Indicator inputs for the serial port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The nRI2 CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. PARALLEL PORT INTERFACE (NOTE 2) nSLCTIN (OD14/OP1 This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. 4)/OD12 Refer to Parallel Port description for use of this pin in ECP and EPP mode.
72
74
nInitiate Output 2 (Note )
nINIT
(OD14/OP1 This output is bit 2 of the printer control register. This 4)/OD12 is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode.
74
76
nAutofeed Output 2 (Note )
nAUTOFD
(OD14/OP1 This output goes low to cause the printer to automatically feed one line after each line is printed. 4)/OD12 The nAUTOFD output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. (OD14/OP1 An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE 4)/OD12 output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. I/OD12 This is a status output from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.
75
77
nStrobe Output 2 (Note )
nSTROBE
59
61
Busy
BUSY
60
62
nAcknowledge
nACK
I/OD12
A low active output from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Another status output from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.
58
60
Paper End
PE
I/OD12
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PIN # TQFP 57 QFP 59
NAME Printer Selected Status
SYMBOL SLCT
BUFFER TYPE I/OD12
DESCRIPTION This high active output from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.
73
75
nError
nERROR
I/OD12
A low on this input from the printer indicates that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Port Data 0-4
69-66, 64
71-68, 66
Port Data 0Port Data 4 Port Data 5 Port Data 6
PD0-4
IOP14/IS
63 62
65 64
PD5 PD6
IOP14 IOP14/ OD12 IOP14 MISC ICLK
Port Data 5 Port Data 6
61 18 92
63 20 94
Port Data 7 14.318 MHz Input Clock Address X/ Interrupt Request B
PD7 CLK14 nADRX
Port Data 7
IRQ_B
The external connection to a single source 14.318 MHz clock. O12/ OD12 Active low address decode out: used to decode a 1, 8, or 16 byte address block. (An external pull-up is required). Refer to Configuration registers CR03, CR08 and CR09 for more information. The interrupt request from a logical device or IRQIN may be output on IRQ_B. Refer to the configuration registers for more information. If EPP or ECP Mode is enabled, this output is pulsed low and released to allow sharing of interrupts. I/O4 This active high input indicates that the power (VCC) is valid. For device operation PWRGD must be active. When PWRGD is inactive, all inputs are disconnected and put into a low power mode; all outputs are put into high impedance. The contents af all registers are preserved as long as VCC is valid. The output driver current drain when PWRGD is inactive mode drops to ISTBY - standby current.
56
58
Power Good
PWRGD
96
98
External IRQIN Interrupt Input
13,70 15,72 Power 4, 10, 11, 6, 12, 13, Ground 12, 14, 15, 14, 16, 17, 23, 45, 25, 47, 65, 93 67, 95 1, 2, 3, 5, 1, 2, 3, 4, Non Connect 6, 7, 8, 9, 5, 7, 8, 9, 16, 21, 24, 10, 11, 18, 23, 26, 99, 100
VCC VSS
This pin is used to steer an interrupt signal from an external device onto one of eight IRQ outputs IRQAH. POWER INTERFACE Positive Supply Voltage. Ground Supply.
IS
NC
Non-Connected Pins
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Note 1: Note 2: Note 3: Note 4:
nRI and the UART interrupts are active when PWRGD is active and the UARTS are either fully powered or in AUTOPOWER DOWN mode. Active (push-pull) output drivers are required on these pins in the enhanced parallel port modes. An external pull-up must be provided for IOCHRDY. The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of PWRGD.
2.2
Buffer Type Summary
Table 2 below describes the buffer types shown in Table 1. All values are specified at Vcc = +3.3v, 10% Table 2 - SP37E760 3.3V Buffer Type Summary BUFFER TYPE IO12 O12 O12PD OD12 O6 OD14 OP14 IOP14 O4 ICLK I IS DESCRIPTION Input/Output. 12mA sink; 6mA source Output. 12mA sink; 6mA source Output. 12mA sink; 6mA source with 30a pull-down Open Drain. 12mA sink Output. 6mA sink; 3mA source Open Drain. 14mA sink Output. 14mA sink; 14mA source. Backdrive Protected Input/Output. 14mA sink; 14mA source. Backdrive Protected Output. 4mA sink; 2mA source Input to Crystal Oscillator Circuit (TTL levels) Input TTL Compatible Input with Schmitt Trigger
2.3
Output Drivers
Active output drivers in the SP37E760 will always achieve the minimum specified DC Electrical Characteristics shown in Table 54. Note: If there is a pull-up on an external node driven by an active output driver the SP37E760 will sink current from the pull-up through the low impedance source.
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Vcc (2)
Vss (4)
PWRGD
POWER MANAGEMENT
MULTI-MODE PARALLEL PORT
nCS nIOR nIOW AEN A0-A10 CONTROL BUS D0-D7 DRQ_A-C nDACK_A_C TC IRQA IRQ_C-F IRQ_H RESET CLOCK IRQIN IOCHRDY 14.318 CLOCK GEN DATA BUS HOST CPU INTERFACE CONFIGURATION REGISTERS 16C550 COMPATIBLE SERIAL PORT 2 16C550 COMPATIBLE SERIAL PORT 1 ADDRESS BUS
nACK nSLCTIN nINIT nAUTOFD nSTROBE BUSY nACK , PE nERROR PD0, PD1, PD2 PD3, PD4 PD5, PD6, PD7
TXD1, nCTS1, nRTS1 RXD1 nDSR1, nDCD1, nRI, nDTR1 TXD2 ,nCTS2 nRTS2 RXD2 nDSR2,nDCD2 nRI2,nDTR2
FIGURE 3 - SP37E760 BLOCK DIAGRAM
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3
FUNCTIONAL DESCRIPTION
Super I/O Registers Table 3 shows the addresses of the various device blocks of the Super I/O immediately after power up. The base addresses must be set in the configuration registers before accessing these devices. The base addresses of the Serial and Parallel Ports can be moved via the configuration registers.
3.1
Host Processor Interface
The host processor communicates with the SP37E760 using the Super I/O registers. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. Table 3 - SP37E760 Block Addresses BLOCK NAME NOTES Configuration Write only; Note 1 Serial Port Com 1 Disabled at power up; Note 2 Serial Port Com 2 Disabled at power up; Note 2 Parallel Port Disabled at power up; Note 2
ADDRESS 3F0, 3F1 or 370, 371 Base +[0:7] Base1 +[0:7] Base2 +[0:7] Base +[0:3] all modes Base +[4:7] for EPP Base +[400:403] for ECP
Note 1: Configuration registers can only be modified in the configuration state, refer to section CONFIGURATION on page 45 for more information. All logical blocks in the SP37E760 can operate normally in the Configuration State. Note 2: The base addresses must be set in the configuration registers before accessing the logical device blocks.
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4
SERIAL PORT (UART)
The SP37E760 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTs perform serial-to-parallel conversion on received characters and parallelto-serial conversion on transmit characters. The data rates are independently programmable from 115.2K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the SP37E760 Configuration Registers for information on disabling, powering down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". When OUT2 is a logic "0" the UART Interrupt is disabled.
4.1
Register Description
Addressing of the accessible registers of the Serial Port is shown below (Table 4). The base addresses of the serial ports are defined by the configuration registers (see section CONFIGURATION on page 45). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The SP37E760 contains two serial ports, each of which contain a register set as described below.
Table 4 - Addressing the Serial Port DLAB1 A2 A1 A0 REGISTER NAME 0 0 0 0 Receive Buffer (read) 0 0 0 0 Transmit Buffer (write) 0 0 0 1 Interrupt Enable (read/write) X 0 1 0 Interrupt Identification (read) X 0 1 0 FIFO Control (write) X 0 1 1 Line Control (read/write) X 1 0 0 Modem Control (read/write) X 1 0 1 Line Status (read/write) X 1 1 0 Modem Status (read/write) X 1 1 1 Scratchpad (read/write) 1 0 0 0 Divisor LSB (read/write) 1 0 0 1 Divisor MSB (read/write) Note1: DLAB is Bit 7 of the Line Control Register
4.1.1
RECEIVE BUFFER REGISTER (RB)
The Receive Buffer register (Address Offset = 0H, DLAB = 0, READ ONLY) holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit character which is transferred to the Receive Buffer register. The shift register is not accessible. 4.1.2
TRANSMIT BUFFER REGISTER (TB)
The Transmit Buffer register (Address Offset = 0H, DLAB = 0, WRITE ONLY) contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data character to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete.
4.1.3
INTERRUPT ENABLE REGISTER (IER)
The lower four bits of the Interrupt Enable register (Address Offset = 1H, DLAB = 0, READ/WRITE) control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, by setting the appropriate bits of this register to a high selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the SP37E760. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below.
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4.1.3.1 ERDAI, Bit 0 The ERDAI bit enables the Received Data Available Interrupt (and time-out interrupts in the FIFO mode) when set to logic "1". 4.1.3.2 ETHREI, Bit 1 The ETHREI bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". 4.1.3.3 ELSI, Bit 2 The ELSI bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. 4.1.3.4 EMSI, Bit 3 The EMSI bit enables the MODEM Status Interrupt when set to logic "1". An MSI is caused when one of the Modem Status Register bits changes state. 4.1.3.5 Reserved, Bits 4 - 7 Bits 4 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
4.1.4
INTERRUPT IDENTIFICATION REGISTER (IIR)
By accessing the Interrupt Identification register (Address Offset = 2H, DLAB = X, READ), the host CPU can determine the highest priority interrupt and its source. Four levels of interrupt priority exist. They are in descending order of priority: 1. 2. 3. 4. Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to the Interrupt Control Table, Table 5). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. 4.1.4.1 Interrupt Pending, Bit 0 The Interrupt Pending bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. 4.1.4.2 Interrupt ID, Bits 1 - 2 The Interrupt ID bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table (Table 5). 4.1.4.3 Time-Out, Bit 3 In non-FIFO mode, the Time-Out bit is a logic "0". In FIFO mode the Time-Out bit is set along with bit 2 when a timeout interrupt is pending. 4.1.4.4 Reserved, Bits 4 - 5 Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read. 4.1.4.5 FIFOs Enabled, Bits 6 - 7 The FIFOs Enabled bits are set when the FIFO CONTROL Register bit 0 equals 1.
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Table 5 - Interrupt Control FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT BIT BIT 2 1 0 0 0 1 1 1 0 INTERRUPT SET AND RESET FUNCTIONS PRIORITY LEVEL Highest INTERRUPT TYPE None Receiver Line Status INTERRUPT SOURCE None Overrun Error, Parity Error, Framing Error or Break Interrupt Receiver Data Available INTERRUPT RESET CONTROL Reading the Line Status Register
0
1
0
0
Second
Received Data Available Character Time-out Indication
1
1
0
0
Second
0
0
1
0
Third
Transmitter Holding Register Empty
0
0
0
0
Fourth
MODEM Status
No Characters Have Been Removed From or Input to the RCVR FIFO during the last 4 Character times and there is at least 1 character in it during this time Reading the IIR Transmitter Register (if Source Holding Register Empty of Interrupt) or Writing the Transmitter Holding Register Reading the Clear to Send MODEM Status or Data Set Ready or Ring Register Indicator or Data Carrier Detect
Read Receiver Buffer or the FIFO drops below the trigger level. Reading the Receiver Buffer Register
4.1.5
FIFO CONTROL REGISTER (FCR)
The FIFO Control register (Address Offset = 2H, DLAB = X, WRITE) appears at the same location as the IIR. This register is used to enable and clear the FIFOs and set the RCVR FIFO trigger level. Note: DMA is not supported. 4.1.5.1 FIFO Enable, Bit 0 Setting the FIFO Enable bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. 4.1.5.2 RCVR FIFO Reset, Bit 1 Setting the RCVR FIFO Reset bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. 4.1.5.3 XMIT FIFO Reset, Bit 2 Setting the XMIT FIFO Reset bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing.
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4.1.5.4 DMA Mode Select, Bit 3 Writing to the DMA Mode Select bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. 4.1.5.5 Reserved, Bits 4 - 5 Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read. 4.1.5.6 RCVR Trigger, Bits 6 - 7 The RCVR Trigger bits are used to set the trigger level for the RCVR FIFO interrupt (Table 6). Table 6 - RCVR Trigger Encoding RCVR RCVR FIFO Trigger Level (BYTES) TRIGGER Bit 7 0 0 1 1 Bit 6 0 1 0 1 1 4 8 14
4.1.6
LINE CONTROL REGISTER (LCR)
The Line Control register (Address Offset = 3H, DLAB = 0, READ/WRITE) contains the formatting information for the serial line. 4.1.6.1 Word Length Select, Bits 0 - 1 The Word Length Select bits specify the number of bits in each transmitted or received serial character. Note: the Start, Stop and Parity bits are not included in the word length. The encoding of the Word Length bits is shown in Table 7. Table 7 - Word Length Encoding WORD LENGTH SELECT WORD LENGTH (Bits) Bit 1 0 0 1 1 Bit 0 0 1 0 1 5 6 7 8
4.1.6.2 Stop Bits, Bit 2 The Stop Bits bit specifies the number of stop bits in each transmitted or received serial character. Table 8 describes the Stop Bits encoding. Table 8 - STOP Bit Encoding STOP BITS WORD NUMBER OF LENGTH STOP BITS (Bit 2) 0 0 1 1 1 5 Bits 6 Bits 7 Bits 8 Bits 1 1.5 2 2 2
Note: The receiver ignores stop bits beyond the first, regardless of the number of stop bits used in transmitting.
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4.1.6.3 Parity Enable, Bit 3 When the Parity Enable bit is a logic "1" a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed. 4.1.6.4 Even Parity Select, Bit 4 When the Even Parity Select (EPS) bit is a logic "0" and the Parity Enable is a logic "1", an odd number of logic "1"'s is transmitted or checked in the data word and the parity bit. When the Parity Enable is a logic "1" and the EPS bit is a logic "1" an even number of bits is transmitted and checked. 4.1.6.5 Stick Parity, Bit 5 When the Stick Parity bit is a logic "1" and the Parity Enable is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by the EPS bit. 4.1.6.6 Set Break, Bit 6 When the Set Break Control bit is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there until reset by a low level bit 6, regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. 4.1.6.7 DLAB, Bit 7 The Divisor Latch Access Bit must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
4.1.7
MODEM CONTROL REGISTER (MCR)
The Modem Control register (Address Offset = 4H, DLAB = X, READ/WRITE) manages the interface for the MODEM, data set, or device emulating a MODEM. 4.1.7.1 Data Terminal Ready, Bit 0 The Data Terminal Ready bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1". Request To Send, Bit 1 The Request To Send bit controls the Request To Send (nRTS) output. . When bit 1 is set to a logic "1", the nRTS output is forced to a logic "0". When bit 1 is a logic "0", the nRTS output is forced to a logic "1". 4.1.7.2 OUT1, Bit 2 The OUT1 bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. 4.1.7.3 OUT2, Bit 3 The OUT2 bit is used to enable the UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state; i.e, disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. 4.1.7.4 Loop, Bit 4 The Loop bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occurs: 1. 2. 3. 4. 5. 6. 7. The TXD is set to the Marking State (logic "1"). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI and DCD) respectively. The Modem Control output pins are forced inactive. Data that is transmitted is immediately received.
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The Loopback feature allows the processor to verify the transmit and receive data paths of the Serial Port. The receiver and the transmitter interrupts are fully operational in loopback mode. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. 4.1.7.5 Reserved, Bits 5 - 7 Bits 5 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
4.1.8
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE 4.1.8.1 Data Ready, Bit 0 Data Ready (DR) is set to a logic "1" whenever a complete received data character has been transferred into the Receiver Buffer Register or the FIFO. DR is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. 4.1.8.2 Overrun Error, Bit 1 The Overrun Error (OE) bit indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register: the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition and reset whenever the Line Status Register is read. 4.1.8.3 Parity Error, Bit 2 The Parity Error (PE) bit indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. 4.1.8.4 Framing Error, Bit 3 The Framing Error (FE) bit indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this `start' bit twice and then takes in the `data'. 4.1.8.5 Break Interrupt, Bit 4 The Break Interrupt (BI) bit is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: LSR Bits 1 through 4 produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. 4.1.8.6 Transmitter Holding Register Empty, Bit 5 The Transmitter Holding Register Empty (THRE) bit indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is read-only.
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4.1.8.7 Transmitter Empty, Bit 6 The Transmitter Empty (TEMT) bit is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is read-only. In the FIFO mode this bit is set whenever the THR and TSR are both empty. 4.1.8.8 RCVR FIFO Error, Bit 7 The RCVR FIFO Error bit is permanently set to logic "0" in the 450 mode. In the FIFO mode this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO.
4.1.9
MODEM STATUS REGISTER (MSR)
The Modem Status register (Address Offset = 6H, DLAB = X, READ/WRITE) provides the current state of the control lines from the MODEM or peripheral device. In addition to this current state information, four bits of the MODEM Status Register provide state change information. These four bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. 4.1.9.1 Delta Clear To Send, Bit 0 The Delta Clear To Send (DCTS) bit indicates that the nCTS input to the chip has changed state since the last time the MSR was read. 4.1.9.2 Delta Data Set Ready, Bit 1 The Delta Data Set Ready (DDSR) bit indicates that the nDSR input has changed state since the last time the MSR was read. 4.1.9.3 Trailing Edge Of Ring Indicator, Bit 2 The Trailing Edge of Ring Indicator (TERI) bit indicates that the nRI input has changed from logic "0" to logic "1". 4.1.9.4 Delta Data Carrier Detect, Bit 3 The Delta Data Carrier Detect (DDCD) bit indicates that the nDCD input to the chip has changed state. Note: Whenever bits 0, 1, 2, or 3 are set to a logic "1", a MODEM Status Interrupt is generated. 4.1.9.5 Clear To Send, Bit 4 The Clear To Send bit is the complement of the Clear To Send input (nCTS). If the Loop bit of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. 4.1.9.6 Data Set Ready, Bit 5 The Data Set Ready bit is the complement of the Data Set Ready input (nDSR). If the Loop bit of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. 4.1.9.7 Ring Indicator, Bit 6 The Ring Indicator bit is the complement of the Ring Indicator input (nRI). If the Loop bit of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. 4.1.9.8 Data Carrier Detect, Bit 7 The Data Carrier Detect bit is the complement of the Data Carrier Detect input (nDCD). If the Loop bit of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR.
4.1.10
SCRATCHPAD REGISTER (SCR)
The Scratchpad register (Address Offset =7H, DLAB =X, READ/WRITE) has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily.
4.1.11 PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES
The internal Baud Rate Generator (BRG) using the Programmable Baud Rate Generator Divisor Latches DDL and DDM (Address Offset = 0 and 1, DLAB = 1, READ/WRITE) is capable of taking any clock input (DC to 3 MHz) and
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dividing it by any divisor from 1 to 65535. The Baud Rate Generator output is 16x the baud rate. Two 8-bit latches store the divisor in 16-bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the DDL and DDM registers the BRG clock is divided by 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the clock is divided by 2 with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 9 shows the baud rates possible with a 1.8462 MHz clock. Table 9 - Baud Rates Using 1.8462 MHz Clock DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800 DIVISOR USED TO GENERATE 16X CLOCK 2307 1538 1049 858 769 384 192 96 64 58 48 32 24 16 12 6 3 2 1 32770 32769 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL* 0.03 0.03 0.005 0.01 0.03 0.16 0.16 0.16 0.16 0.5 0.16 0.16 0.16 0.16 0.16 0.16 0.16 1.6 0.16 0.16 0.16 CROC: BIT 7 OR 6 X X X X X X X X X X X X X X X X X X X 1 1
4.1.12 THE AFFECTS OF RESET ON THE UART REGISTERS
The RESET Function (Table 10) details the affects of RESET on each of the Serial Port registers. Table 10 - RESET Function RESET CONTROL RESET RESET RESET RESET RESET RESET RESET RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR
REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE)
RESET STATE All bits low Bit 0 is high; Bits 1 - 7 low All bits low All bits low All bits low All bits low except 5 - 6 high Bits 0 - 3 low; Bits 4 - 7 input High Low Low Low
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REGISTER/SIGNAL OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO
RESET CONTROL RESET RESET RESET RESET RESET/FCR1*FCR0/_FCR0 RESET/FCR1*FCR0/_FCR0
RESET STATE High High High High All bits low All bits low
4.2
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: 1. 2. 3. 4. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. The data ready bit (LSR bit 0)is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts occur as follows: 1. A FIFO time-out interrupt occurs if all the following conditions exist: at least one character is in the FIFO The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay.) The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate). When a time-out interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. When a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after the CPU reads the RCVR FIFO.
2. 3. 4. 5.
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: 1. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmit FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
2.
Character time-out and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
4.3
FIFO Polled Mode Operation
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows:
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1. 2. 3. 4. 5.
Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. Table 11 - Individual UART Channel Register Summary REGISTER SYMBOL REGISTER NAME BIT 0 BIT 1 Receive Buffer Register RBR Data Bit 0 (Note Data Bit 1 (Read Only) 1) Transmitter Holding Register (Write Only) Interrupt Enable Register THR IER Data Bit 0 Enable Received Data Available Interrupt (ERDAI) "0" if Interrupt Pending FIFO Enable Word Length Select Bit 0 (WLS0) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send (DCTS) Bit 0 Bit 0 Bit 8 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt ID Bit RCVR FIFO Reset Word Length Select Bit 1 (WLS1) Request to Send (RTS) Overrun Error (OE) Delta Data Set Ready (DDSR) Bit 1 Bit 1 Bit 9
REGISTER ADDRESS* ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0 ADDR = 2 ADDR = 2 ADDR = 3
Interrupt Ident. Register (Read Only) FIFO Control Register (Write Only) Line Control Register
IIR FCR LCR
ADDR = 4 ADDR = 5 ADDR = 6 ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1
MODEM Control Register Line Status Register MODEM Status Register Scratch Register (Note 4) Divisor Latch (LS) Divisor Latch (MS)
MCR LSR MSR SCR DDL DLM
*DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. Table 12 - Individual UART Channel Register Summary Continued BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 3 Enable MODEM Status Interrupt (EMSI) Data Bit 4 0 Data Bit 5 0 Data Bit 6 0 Data Bit 7 0
BIT 2 Data Bit 2 Data Bit 2
Enable Receiver Line Status Interrupt (ELSI)
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BIT 2 BIT 3 Interrupt ID Bit Interrupt ID Bit 0 (Note 5) XMIT FIFO Reset Number of Stop Bits (STB) OUT1 (Note 3) Parity Error (PE) DMA Mode Select (Note 6) Parity Enable (PEN) OUT2 (Note 3) Framing Error (FE)
BIT 4 0
BIT 5
Reserved
Reserved
BIT 6 BIT 7 FIFOs Enabled FIFOs (Note 5) Enabled (Note 5) RCVR Trigger RCVR Trigger LSB MSB Set Break Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO (Note 5) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
Even Parity Stick Parity Select (EPS) Loop Break Interrupt (BI) 0 Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13
0 Transmitter Empty (TEMT) (Note 2) Ring Indicator (RI) Bit 6 Bit 6 Bit 14
Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10 Note 3: Note 4: Note 5: Note 6:
Delta Data Carrier Detect (DDCD) Bit 3 Bit 3 Bit 11
Clear to Send (CTS) Bit 4 Bit 4 Bit 12
This bit no longer has a pin associated with it. When operating in the XT mode, this register is not available. These bits are always zero in the non-FIFO mode. Writing a one to this bit has no effect. DMA modes are not supported in this chip.
4.4
4.4.1
Notes On Serial Port FIFO Mode Operation
GENERAL
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
4.4.2
TX AND RX FIFO OPERATION
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun
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Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a time-out interrupt. The time-out interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The time-out interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256K baud).
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5
PARALLEL PORT
The SP37E760 incorporates an IBM XT/AT compatible parallel port. The SP37E760 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the SP37E760 Configuration Registers and the following hardware configuration description for information on disabling, powering down, changing the base address, and selecting the mode of operation of the parallel port. The SP37E760 also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map and bit encoding of the Parallel Port registers is shown in Table 13; the Parallel Port Connector is shown in Table 14. Table 13 - Parallel Port Registers BASE ADDRESS OFFSET DATA PORT1 STATUS PORT1 CONTROL PORT1 EPP ADDR PORT2,3 EPP DATA PORT 02,3 EPP DATA PORT 12,3 EPP DATA PORT 22,3 EPP DATA PORT 32,3 Note 2 Note 3 Note
1
00H 01H 02H 03H 04H 05H 06H 07H
D1 D0 PD0 PD1 TMOUT 0 STROB AUTOFD E PD0 PD1 PD0 PD0 PD0 PD0 PD1 PD1 PD1 PD1
D2 PD2 0 nINIT PD2 PD2 PD2 PD2 PD2
D3 PD3 nERR SLC PD3 PD3 PD3 PD3 PD3
D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4
D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5
D7 D6 PD6 PD7 nACK nBUSY 0 0 PD6 PD6 PD6 PD6 PD6 AD7 PD7 PD7 PD7 PD7
These registers are available in all modes. These registers are only available in EPP mode. For EPP mode, IOCHRDY must be connected to the ISA bus. Table 14 - Parallel Port Connector
HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17
PIN # TQFP 75 69-66,64-61 60 59 58 57 74 73 72 71 QFP 77 71-68, 66-63 62 61 60 59 76 75 74 73 STANDARD nSTROBE PD<0:7> nACK BUSY PE SLCT nAUOTFD nERROR nINIT nSLCTIN EPP nWrite PData<0:7> Intr nWait (NU) (NU) nDatastb (NU) (NU) nAddrstrb ECP nStrobe PData<0:7> nAck Busy, PeriphAck(3) PError, nAckReverse(3) Select nAutoFd, HostAck(3) nFault(1) nPeriphRequest(3) nInit(1) nReverseRqst(3) nSelectIn(1,3)
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(1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.09, Jan. 7, 1993. This document is available from Microsoft.
5.1
5.1.1
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
DATA PORT
ADDRESS OFFSET = 00H The Data Port is located at an offset of `00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus with the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
5.1.2
STATUS PORT
ADDRESS OFFSET = 01H The Status Port is located at an offset of `01H' from the base address. The contents of this register are latched for the duration of an nIOR read cycle. The bits of the Status Port are defined as follows: 5.1.2.1 BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic "0" means that no time out error has occurred; a logic "1" means that a time out error has been detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect. BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic "0" means an error has been detected; a logic "1" means no error has been detected.
5.1.2.1.1 BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic "1" means the printer is on line; a logic "0" means it is not selected.
5.1.2.1.2 BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic "1" indicates a paper end; a logic "0" indicates the presence of paper. 5.1.2.2 BIT 6 nACK - nACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic "1" means that it is still processing the last character or has not received the data. 5.1.2.3 BIT 7 nBUSY - nBUSY The complement of the level on the nBUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic "1" means that it is ready to accept the next character.
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5.1.3
CONTROL PORT
ADDRESS OFFSET = 02H The Control Port is located at an offset of `02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. 5.1.3.1 BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. 5.1.3.2 BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. after each line is printed. A logic 0 means no autofeed. 5.1.3.3 BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. 5.1.3.4 BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic "1" on this bit selects the printer; a logic "0" means the printer is not selected. 5.1.3.5 BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. 5.1.3.6 BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is valid in extended mode only (CR#1<3>=0). In printer mode, the direction is always out regardless of the state of this bit. In bi-directional mode, a logic "0" means that the printer port is in output mode (write); a logic "1" means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written.
A logic "1" causes the printer to generate a line feed
5.1.4
EPP ADDRESS PORT
ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of `03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP ADDRESS WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 PD7 ports are read, the leading edge of IOR causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode.
5.1.5
EPP DATA PORT 0
ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of `04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP DATA WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode.
5.1.6
EPP DATA PORT 1
ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of `05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
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5.1.7
EPP DATA PORT 2
ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of `06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
5.1.8
EPP DATA PORT 3
ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of `07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
5.2
EPP 1.9 OPERATION
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10sec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted.
5.2.1
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e. a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated. 5.2.2 EPP 1.9 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP 1.9 Write Data or Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.
Write Sequence of operation 1. 2. 3. 4. 5. 6. 7. The host selects an EPP register, places data on the SData bus and drives nIOW active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. A) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. B) The chip latches the data from the SData bus for the PData bus and asserts (releases) IOCHRDY allowing the host to complete the write cycle. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
8. 9.
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5.2.3
EPP 1.9 READ
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.
Read Sequence of Operation The host selects an EPP register and drives nIOR active. The chip drives IOCHRDY inactive (low). If WAIT is not asserted, the chip must wait until WAIT is asserted. The chip tri-states the PData bus and deasserts nWRITE. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 6. Peripheral drives PData bus valid. 7. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 8. A) The chip latches the data from the PData bus for the SData bus, deasserts DATASTB or nADDRSTRB, this marks the beginning of the termination phase. B) The chip drives the valid data onto the SData bus and asserts (releases) IOCHRDY allowing the host to complete the read cycle. 9. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated. 10. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle. 1. 2. 3. 4. 5.
5.3
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to the end of the cycle nIOR or nIOW deasserted). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.
5.3.1
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read.
5.3.2
EPP 1.7 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. 2. The host selects an EPP register, places data on the SData bus and drives nIOW active. 3. The chip places address or data on PData bus. 4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. 5. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. 6. When the host deasserts nI0W the chip deasserts nDATASTB or nADDRSTRB and latches the data from the SData bus for the PData bus.
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7.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
5.3.3
EPP 1.7 READ
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. 2. The host selects an EPP register and drives nIOR active. 3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 4. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. 5. The Peripheral drives PData bus valid. 6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 7. When the host deasserts nI0R the chip deasserts nDATASTB or nADDRSTRB. 8. Peripheral tri-states the PData bus. 9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 15 - EPP Pin Descriptions EPP SIGNAL nWRITE PD<0:7> INTR WAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE DESCRIPTION O This signal is active low. It denotes a write operation. I/O Bi-directional EPP byte wide address and data bus. I This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP). I This signal is active low. It is driven inactive as a positive acknowledgment from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. O This signal is active low. It is used to denote data read or write operation. O This signal is active low. When driven active, the EPP device is reset to its initial operational mode. O This signal is active low. It is used to denote address read or write operation. I Same as SPP mode. I Same as SPP mode.
DATASTB RESET
nData Strobe nReset
Same as SPP mode. This output shows the direction of the data transfer on the parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress. Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low.
ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status NERR Error PDIR Parallel Port Direction
I O
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5.4
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. * High performance half-duplex forward and reverse channel * Interlocked handshake, for fast reliable transfer * Optional single byte RLE compression for improved throughput (64:1) * Channel addressing for low-cost peripherals * Maintains link and data layer separation * Permits the use of active output drivers * Permits the use of adaptive signal timing * Peer-to-peer capability
5.4.1
VOCABULARY
The following terms are used in this document: assert When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward Host to Peripheral communication. reverse Peripheral to Host communication. Pword A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8 bits. 1 A high level 0 A low level These terms may be considered synonymous: PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.09, Jan 7, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is shown in Table 16. Table 16 - ECP Registers D5 D4 D3 PD5 PD4 PD3 Address or RLE field PError Select nFault Direction ackIntEn SelectIn Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 1 0 0 0 0 nErrIntrEn dmaEn
data ecpAFifo2 dsr1 dcr1 cFifo2 ecpDFifo2 tFifo2 cnfgA cnfgB ecr Note1 2 Note
D7 PD7 Addr/RLE nBusy 0
D6 PD6 nAck 0
D2 PD2 0 nInit
D1 PD1 0 autofd
D0 PD0 0 strob e
0 compress
0 intrValue MODE
0 0 serviceIntr
0 0 full
0 0 empt y
These registers are available in all modes. All FIFOs use one common 16 byte FIFO.
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5.4.2
ISA IMPLEMENTATION STANDARD
This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.09, Jan.7, 1993. This document is available from Microsoft.
5.4.3
DESCRIPTION
The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. Table 17 - ECP Pin Descriptions TYPE DESCRIPTION O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). I/O Contains address or data or RLE data. I Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. I This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. I Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. I Indicates printer on line. O Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. I Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. O Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. O Always deasserted in ECP mode.
NAME nStrobe Pdata 7:0 Nack PeriphAck (Busy)
Perror (nAckReverse)
Select NAutoFd (HostAck)
NFault (nPeriphRequest)
NInit
NSelectIn
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5.4.4
REGISTER DEFINITIONS
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr (Table 19). Table 18 lists these dependencies. Operation of the devices in modes other that those specified is undefined. Table 18 - ECP Register Definitions ADDRESS (Note 1) ECP MODES FUNCTION data +000h R/W 000-001 Data Register ecpAFifo +000h R/W 011 ECP FIFO (Address) dsr +001h R/W All Status Register dcr +002h R/W All Control Register cFifo +400h R/W 010 Parallel Port Data FIFO ecpDFifo +400h R/W 011 ECP FIFO (DATA) tFifo +400h R/W 110 Test FIFO cnfgA +400h R 111 Configuration Register A cnfgB +401h R/W 111 Configuration Register B ecr +402h R/W All Extended Control Register Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. NAME Table 19 - Mode Descriptions DESCRIPTION (Refer to ECR Register Description) SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) (Reserved) Test mode Configuration mode
MODE 000 001 010 011 100 101 110 111
5.4.4.1 DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of `00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet . 5.4.4.2 DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H
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The Status Port is located at an offset of `01H' from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: 5.4.4.2.1 BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. 5.4.4.2.2 BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. 5.4.4.2.3 BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. 5.4.4.2.4 BIT 6 nAck
The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.
5.4.4.2.5 BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register. 5.4.4.3 DEVICE CONTROL REGISTER (dcr) ADDRESS OFFSET = 02H The Control Register is located at an offset of `02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. 5.4.4.3.1 BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. 5.4.4.3.2 BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. 5.4.4.3.3 BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. 5.4.4.3.4 BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. 5.4.4.3.5 BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. 5.4.4.3.6 BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). 5.4.4.3.7 Bits 6 and 7 during a read are a low level, and cannot be written. 5.4.4.4 cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010
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Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. 5.4.4.5 ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 5.4.4.6 tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. 5.4.4.7 cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) 5.4.4.8 cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 5.4.4.8.1 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! 5.4.4.8.2 BIT 6 intrValue Returns the value on the ISA iRq line to determine possible conflicts. 5.4.4.8.3 BITS 5:0 Reserved During a read are a low level. These bits cannot be written.
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5.4.4.9 ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions (Table 20). 5.4.4.9.1 BITS 7,6,5 These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a "1" to a "0". This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. 5.4.4.9.2 BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is "0"). 0: Disables DMA unconditionally. 5.4.4.9.3 BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a "1" by hardware, it must be reset to "0" to re-enable the interrupts. Writing this bit to a "1" will not cause an interrupt. case dmaEn=1: During DMA (this bit is set to a "1" when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to "1" whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to "1" whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.
5.4.4.9.4 BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. 5.4.4.9.5 BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data. Table 20 - Extended Control Register MODE Standard Parallel Port mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).
R/W 000:
001:
010:
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R/W 011:
100: 101: 110: 111:
MODE ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register CR4. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull).
5.4.5
OPERATION
5.4.5.1 Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ECP reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above. 5.4.5.2 ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: Set Set Set Set Direction = 0, enabling the drivers. strobe = 0, causing the nStrobe signal to default to the deasserted state. autoFd = 0, causing the nAutoFd signal to default to the deasserted state. mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty . ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000.
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5.4.5.3 Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. 5.4.5.4 Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8-bit commands (Table 21). When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 21 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) Data Compression D7 D[6:0] 0 Run-Length Count (0-127) (mode 0011 0X00 only) 1 Channel Address (0-127) The SP37E760 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided. 5.4.5.5 Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes. 5.4.5.6 ISA Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals. 5.4.5.7 Interrupts
The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold. The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. An interrupt is generated when: 1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC is received. 2. For Programmed I/O:
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a.
When serviceIntr is "0", dmaEn is "0", direction is "0" and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to "0" whenever there are writeIntrThreshold or more free bytes in the FIFO.
3. 4.
b.(1)When serviceIntr is 0, dmaEn is 0, direction is "1" and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to "0" whenever there are readIntrThreshold or more bytes in the FIFO. When nErrIntrEn is "0" and nFault transitions from high to low or when nErrIntrEn is set from "1" to "0" and nFault is asserted. When ackIntEn is "1" and the nAck signal transitions from a low to a high.
5.4.5.8 FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or PDRQ depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. 5.4.5.9 DMA TRANSFERS
Notes: PDRQ - Currently selected Parallel Port DRQ channel nPDACK - Currently selected Parallel Port DACK channel PINTR - Currently selected Parallel Port IRQ channel
5.4.5.9.1 Typical DMA Mode Transfers DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to "1" and serviceIntr to "0". The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting nPDACK and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a TC). DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting serviceIntr to 0. dmaEn to 1, followed by setting
5.4.5.9.2 DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral). The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes inactive after nPDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as
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soon as there is one byte in the FIFO. If PDRQ goes inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and serviceIntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to prevent an unwanted cycle). 5.4.5.10 Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same. 5.4.5.11 Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold =(16-) data bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the FIFO in a single burst. 5.4.5.12 Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16-) free bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to . (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO.
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6
AUTO POWER MANAGEMENT
Power management is provided for the following SP37E760 logical devices: UART1, UART2 and the Parallel Port. For each logical device two types of power management are provided; direct powerdown and auto powerdown. Direct powerdown is controlled by the powerdown bits in the configuration registers. One bit is provided for each logical device. Auto powerdown can be enabled for each logical device by setting the Auto Powerdown Enable bits in the configuration registers. In addition, a chip-level hardware powerdown function has been provided through the PWRGD pin. Refer to Table 1 and to other descriptions of the PWRGD function, for example section CONFIGURATION, for more information.
6.1
Pin Behavior
The SP37E760 is specifically designed for portable PC systems where power conservation is a primary concern. Consequently, the behavior of the device pins during powerdown are very important.
6.1.1
SYSTEM INTERFACE PINS
Table 22 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Input pins are "Disabled" to prevent them from causing currents internal to the SP37E760 when they have indeterminate input values. Table 22 - State of System Pins in Auto Powerdown SYSTEM PINS STATE IN AUTO POWERDOWN Input Pins IOR IOW A[0:9] D[0:7] RESET IDENT DACK TC FINTR DB[0:7] FDRQ Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Output Pins Unchanged (low) Unchanged Unchanged (low)
6.2
UART Power Management
Direct UART power management is controlled by the UART1 and UART2 Power Down bits in Configuration Register 2. Refer to section CR02 on page 49 for more information. UART Auto Power Management is enabled by the UART 1 and UART 2 Enable bits in Configuration Register 7 (see section CR07 on page 51). When set, these bits enable the following auto power management features: 1. The transmitter enters auto powerdown when the transmit buffer and transmit shift register are empty. 2. The receiver enters powerdown when the following conditions are all met: Receive FIFO is empty The receiver is waiting for a start bit. While in the powerdown state, the Ring Indicator interrupts are still valid and are activated when the RI inputs change. The UART transmitters exit the powerdown state on a write to the XMIT buffer. The UART receivers exit the auto powerdown state when RXDx changes state. Note:
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6.3
Parallel Port
Direct parallel port power management is controlled by the Parallel Port Power bit in Configuration Register 1. Refer to section CR01 on page 48 for more information. Parallel port Auto Power Management is enabled by the Parallel Port Enable bit in Configuration Register 7 (see section CR07 on page 51). When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into the powerdown state as follows: The EPP logic is in powerdown under any of the following conditions: 1. EPP is not enabled in the configuration registers. 2. EPP is not selected through ecr while in ECP mode. The ECP logic is in powerdown under any of the following conditions: 1. ECP is not enabled in the configuration registers. 2. SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers.
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7
CONFIGURATION
The configuration of the SP37E760 is programmed through hardware selectable Configuration Access Ports that appear when the chip is placed into the configuration state. The SP37E760 logical device blocks, if enabled, will operate normally in the configuration state.
7.1
Configuration Access Ports
The Configuration Access Ports are the CONFIG PORT, the INDEX PORT, and the DATA PORT (Table 23). The base address of these registers is controlled by the nRTS2/SYSOPT pin (see Table 1). To determine the configuration base address, the state of the nRTS2/SYSOPT pin is latched by the falling edge of a hardware reset. If the latched state is a 0, the base address of the Configuration Access Ports is located at address 3F0H; if the latched state is a 1, the base address is located at address 370H. Table 23 - Configuration Access Ports SYSOPT = 0 SYSOPT = 1 0x3F0 0x370 0x3F0 0x370 INDEX PORT + 1
PORT NAME CONFIG PORT INDEX PORT DATA PORT Note1: 2 Note :
TYPE WRITE READ/WRITE1,2 READ/WRITE1
The INDEX and DATA ports are active only when the SP37E760 is in the configuration state. The INDEX PORT is only readable in the configuration state.
7.2
Configuration State
The configuration registers are used to select programmable chip options. The SP37E760 operates in two possible states: the run state and the configuration state. After power up by default the chip is in the run state. To program the configuration registers, the configuration state must be explicitly enabled. Programming the configuration registers typically follows this sequence: 1. 2. 3. Enter the Configuration State, Program the Configuration Register(s), Exit the Configuration State.
7.2.1
ENTERING THE CONFIGURATION STATE
To enter the configuration state write the Configuration Access Key to the CONFIG PORT. The Configuration Access Key is one byte of 55H data. The SP37E760 will automatically activate the Configuration Access Ports following this procedure.
7.2.2
CONFIGURATION REGISTER PROGRAMMING
The SP37E760 contains configuration registers CR00-CR2F. After the SP37E760 enters the configuration state, configuration registers can be programmed by first writing the register index number (00 - 2FH) to the Configuration Select Register (CSR) through the INDEX PORT and then writing or reading the configuration register contents through the DATA PORT. Configuration register access remains enabled until the configuration state is explicitly exited.
7.2.3
EXITING THE CONFIGURATION STATE
To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The SP37E760 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until the configuration state is explicitly re-enabled.
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7.2.4
PROGRAMMING EXAMPLE
The following is a configuration register programming example written in Intel 8086 assembly language. ;-----------------------------. ; ENTER CONFIGURATION STATE | ;-----------------------------` MOV DX,3F0H MOV AX,055H OUT DX,AL ;-----------------------------. ; CONFIGURE REGISTERS CR0-CRx | ;-----------------------------` MOV DX,3F0H MOV AL,00H OUT DX,AL ;Point to CR0 MOV DX,3F1H MOV AL,3FH OUT DX,AL ;Update CR0 ; MOV DX,3F0H MOV AL,01H OUT DX,AL ;Point to CR1 MOV DX,3F1H MOV AL,9FH OUT DX,AL ;Update CR1 ; ; Repeat for all CRx registers ; ;-----------------------------. ; EXIT CONFIGURATION STATE | ;-----------------------------` MOV DX,3F0H MOV AX,AAH OUT DX,AL
7.2.5
CONFIGURATION SELECT REGISTER (CSR)
The Configuration Select Register can only be accessed when the SP37E760 is in the configuration state. The CSR is located at the INDEX PORT address and must be initialized with configuration register index before the register can be accessed using the DATA PORT.
7.3
Configuration Registers Description
The configuration registers are set to their default values at power up (Table 24) and are not affected by RESET, except where noted in the register descriptions that follow. Table 24 - Configuration Registers
DEFAULT INDEX 28H 9CH 88H 70H 00H 00H CR00 CR01 CR02 DB7 Valid Lock CRx UART2 PWR DB6 DB5 Reserved Reserved Reserved Reserved EPP Type MIDI 2 MIDI 1 Reserved DB4 DB3 Reserved PP MODE UART1 PWR ADRX IRQ_B Reserved DB2 Reserved PP PWR DB1 DB0 Reserved Reserved Reserved Reserved PWRGD
CR03 ADRX/ IRQ_B CR04 CR05 Reserved
PP Ext. Modes
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DEFAULT INDEX FFH 00H 00H 00H 00H 00H 02H CR06 CR07 CR08 CR09 CR0A CR0B CR0C
DB7
DB6
DB5
DB4
DB3 Reserved
DB2 Reserved
DB1
DB0
Auto Power Management ADRA7 ARDA6 ADRA5 ADRA4 Reserved Reserved Reserved UART 2 Speed UART 1 Speed UART 2 Mode 0 ADRx Config Cntrl Reserved Reserved
Reserved 0 0 ADRA9 0 ADRA8
ADRA10
ECP FIFO Threshold UART 2 Duplex UART 2 XMIT Polarity UART 2 RCV Polarity
28H Revision 00H 00H 80H 00H 03H 00H 80H 00H 3CH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 03H 00H 00H
CR0D CR0E CR0F CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR1D CR1E CR1F CR20 CR21CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR2A CR2B CR2C CR2D CR2E CR2F Reserved Reserved Reserved Serial 1 IRQ Reserved Reserved Reserved Test 7 Test 15 Test 23 Test 6 Test 14 Test 22 Test 5 Test 13 Test 21 Test 4 Test 12 Test 20
Device ID Device Revision Test 3 Test 11 Test 19 Reserved Test 2 Test 10 Test 18 Test 1 Test 9 Test 17 Test 0 Test 8 Test 16
Reserved
UART1 FIFO Control Shadow UART2 FIFO Control Shadow
Reserved
Reserved Reserved Reserved 0 Reserved Parallel Port - ADR[9:2] Serial Port 1 - ADR[9:3] Serial Port 2 - ADR[9:3] Parallel Port DRQ Parallel Port IRQ Serial 2 IRQ IRQIN IRQ Reserved SCE Base I/O ADDR[10:3] Serial Port 2 DMA Channel Select Reserved Software Select A Software Select B 0 0 0
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7.3.1
CR00
CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. The default value of this register after power up is 28H (Table 25). Table 25 - CR00 BIT NO. 0:2 3 4,5,6 7 BIT NAME Reserved
Reserved
Reserved Valid
DESCRIPTION Read Only. A read returns 0 Read Only. Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0. A high level on this software controlled bit can be used to indicate that a valid configuration cycle has occurred. The control software must take care to set this bit at the appropriate times. Set to zero after power up. This bit has no effect on any other hardware in the chip.
7.3.2
CR01
CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. The default value of this register after power up is 9CH (Table 26). Table 26 - CR01 BIT NO. 0,1 2 3 BIT NAME Reserved Parallel Port Power1 Parallel Port Mode Reserved Reserved Lock CRx DESCRIPTION Read Only. A read returns "0". A high level on this bit, supplies power to the Parallel Port (Default). A low level on this bit puts the Parallel Port in low power mode. Parallel Port Mode. A high level on this bit, sets the Parallel Port for Printer Mode (Default). A low level on this bit enables the Extended Parallel port modes. Refer to Bits 0 and 1 of CR4 Read Only. A read returns "1". Read Only. A read returns "0". A high level on this bit enables the reading and writing of CR00 CR2F (Default). A low level on this bit disables the reading and writing of CR00 - CR2F. Note: once the Lock Crx bit is set to "0", this bit can only be set to "1" by a hard reset or power-up reset.
4 5,6 7
Note1:
Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device's base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking.
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7.3.3
CR02
CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. The default value of this register after power up is 88H (Table 27). Table 27 - CR02 BIT NO. 0:2 3 BIT NAME Reserved UART1 Power Down1 DESCRIPTION Read Only. A read returns "0". A high level on this bit, allows normal operation of the Primary Serial Port (Default). A low level on this bit places the Primary Serial Port into Power Down Mode. Read Only. A read returns "0". A high level on this bit, allows normal operation of the Secondary Serial Port, including the SCE block (Default). A low level on this bit places the Secondary Serial Port including the SCE block into Power Down Mode.
4:6 7
Reserved UART2 Power Down1
1 Note :
Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range for the logical device. To disable the host address registers the logical device's base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking.
7.3.4
CR03
CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H. The default value after power up is 70H (Table 28). Table 28 - CR03 BIT NO. 0 BIT NAME PWRGD DESCRIPTION Bit 0 Pin Function 0 PWRGD (default) 1 Reserved Reserved- Read as Zero Reserved - Read as zero Reserved - Read as one Reserved - Read as one Reserved - Read as one Bit - 7 Bit - 2 Pin 92 0 0 Default 0 1 Reserved 1 0 ADRX 1 1 IRQ_B
1 3 4 5 6 7,2
Reserved Reserved Reserved Reserved Reserved ADRx/ IRQ_B
Note1:
See Note2 in section CR05 on page 50.
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7.3.5
CR04
CR04 can only be accessed in the configuration state and after the CSR has been initialized to 04H. The default value after power up is 00H (Table 29). Table 29 - CR04: Parallel and Serial Extended Setup Register BIT NO. 1,0 BIT NAME Parallel Port Extended Modes DESCRIPTION If CR1 bit 3 is a low level then: Standard and Bi-directional Modes (SPP) (default)
Bit 1 0
Bit 0 0
2,3 4
Reserved MIDI 13 MIDI 23
5
6 7 Note1: 2 Note : Note3:
EPP Type Reserved
0 1 EPP Mode and SPP 1 0 ECP Mode2 1 1 ECP Mode & EPP Mode1,2 . Reserved - Read as 0 Serial Clock Select Port 1: A low level on this bit, disables MIDI support, clock = divide by 13 (default). A high level on this bit enables MIDI support, clock = divide by 12. Serial Clock Select Port 2: A low level on this bit, disables MIDI support, clock = divide by 13 (default). A high level on this bit enables MIDI support, clock = divide by 12. 0 = EPP 1.9 (default) 1 = EPP 1.7 Reserved - Read as 0.
In this mode, EPP can be selected through the ecr register of ECP as mode 100. In these modes, 2 drives can be supported directly, 3 or 4 drives must use external 4 drive support. SPP can be selected through the ecr register of ECP as mode 000. MIDI Support: The Musical Instrumental Digital Interface (MIDI) operates at 31.25Kbaud (+/-1%) which can be derived from 125KHz. (24 MHz/12=2 MHz, 2 MHz/16=125 KHz).
7.3.6
CR05
(Reserved). The default value after power up is 00H .
7.3.7
CR06
(Reserved). The default value of this register after power up is FFH.
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7.3.8
CR07
CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. The default value of this register after power up is 00H (Table 30). CR07 controls auto power management. Table 30 - CR07: Auto Power Management and Boot Drive Select BIT NAME DESCRIPTION Reserved Reserved Reserved Parallel Port Enable Read as 0. Read as 0. Read as 0. This bit controls the AUTOPOWER DOWN feature of the Parallel Port. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. This bit controls the AUTOPOWER DOWN feature of the UART2. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. This bit controls the AUTOPOWER DOWN feature of the UART1. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. Read as 0.
BIT NO. 0,1 2 3 4
5
UART 2 Enable
6
UART 1 Enable
7
Reserved
7.3.9 CR08 CR08 can only be accessed in the configuration state and after the CSR has been initialized to 08H. The default value of this register after power up is 00H (Table 31). CR08 contains the lower 4 bits (ADRA7:4) for the ADRx address decoder. Bits D0 - D3 are Reserved. Reserved bits cannot be written and return 0 when read. Table 31 - CR08: ADRx Lower Address Decode D5 D4 D3 D2 D1 ADRA5 ADRA4 Reserved
D7 ADRA7
D6 ADRA6
D0
7.3.10 CR09
CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. The default value of this register after power up is 00H (Table 32). CR09 contains the upper 3 bits (ADRA10:8) of the ADRx address decoder and the ADRx Configuration Control Bits D[7:6]. The ADRx Configuration Control Bits configure the ADRx Address Decoder (Table 33). Table 32 - CR09: ADRx Upper Address Decoder and Configuration D6 D5 D4 D3 D2 D1 ADRx Reserved ADRA10 ADRA9 CONFIGURATION CONTROL D7
D0 ADRA8
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Table 33 - ADRx Configuration Bits ADRx CONFIGURATION CONTROL DESCRIPTION D7 0 0 1 1 D6 0 1 0 1 ADRx disabled 1 Byte decode A[3:0]=0000b 8 Byte block decode A[3:0]=0XXXb 16 byte block decode A[3:0]=XXXXb
Note: Upper Address Decode requirements: nCS = '0' is required to qualify the ADRx output.
7.3.11 CR0A
CR0A can only be accessed in the configuration state and after the CSR has been initialized to 0AH. The default value of this register after power up is 00H (Table 34). CR0A defines the FIFO threshold for the ECP mode parallel port. Bits D[7:4] are Reserved. Reserved Bits cannot be written and return 0 when read. Table 34 - CR0A D5 D4 D3 RESERVED THR3
D7 D6 RESERVED
D2 D1 ECP FIFO THRESHOLD THR2 THR1
D0 THR0
7.3.12
CR0B
CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. The default value of this register after power up is 00H.
7.3.13 CR0C
CR0C can only be accessed in the configuration state and after the CSR has been initialized to 0CH. The default value of this register after power up is 02H (Table 35). CR0C controls the operating mode of the UART. This register is reset to the default state by a POR or a hardware reset. Table 35 - CR0C BIT NO. 0 1 2 DESCRIPTION 0 = RX input active high (default). 1 = RX input active low. UART 2 XMIT 0 = TX output active high. Polarity 1 = TX output active low (default). UART 2 Duplex This bit is used to define the FULL/HALF DUPLEX operation of UART 2. 1 = Half duplex 0 = Full duplex (default) UART 2 MODE UART 2 Mode 543 000 Standard (default) Other Values Reserved UART 1 Speed This bit enables the high speed mode of UART 1. 1 = High speed enabled 0 = Standard (default) BIT NAME UART 2 RCV Polarity
3, 4, 5
6
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BIT NO. 7
BIT NAME UART Speed
DESCRIPTION This bit enables the high speed mode of UART 2. 1 = High speed enabled 0 = Standard (default)
7.3.14 CR0D
CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the SP37E760 Device ID. The default value of this register after power up is 28H.
7.3.15 CR0E
CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. This register is read only. CR0E contains the current SP37E760 Chip Revision Level.
7.3.16 CR0F
CR0F can only be accessed in the configuration state and after the CSR has been initialized to 0FH. The default value of this register after power up is 00H (Table 36). CR0F is a test control register and all bits must be treated as Reserved. Note: all test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 36 - CR0F BIT NAME DESCRIPTION Test 0 Test 1 Test 2 Test 3 RESERVED FOR SMSC USE Test 4 Test 5 Test 6 Test 7
BIT NO. 0 1 2 3 4 5 6 7
7.3.17 CR10
CR10 can only be accessed in the configuration state and after the CSR has been initialized to 10H. The default value of this register after power up is 00H (Table 37) CR10 is a test control register and all bits must be treated as Reserved. NOTE: all test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 37 - CR10 BIT NAME DESCRIPTION Test 8 Test 9 Test 10 Test 11 RESERVED FOR SMSC USE Test 12 Test 13 Test 14 Test 15
BIT NO. 0 1 2 3 4 5 6 7
7.3.18 CR11
CR11 can only be accessed in the configuration state and after the CSR has been initialized to 11H. The default value of this register after power up is 80H (Table 38). CR11 is a test control register and all bits must be treated as
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Reserved. Note: all test modes are reserved for SMSC use. Activating test mode registers may produce undesired results. Table 38 - CR11 BIT NAME DESCRIPTION Test 16 Test 17 Test 18 Test 19 RESERVED FOR SMSC USE Test 20 Test 21 Test 22 Test 23
BIT NO. 0 1 2 3 4 5 6 7
7.3.19 CR12 - CR13
CR12 - CR13 are reserved and Read Only. The default value of these registers after power up is 00H.
7.3.20 CR14
(Reserved).
7.3.21 CR15
CR15 can only be accessed in the configuration state and after the CSR has been initialized to 15H. CR15 shadows the bits in the write-only UART1 run-time FCR register (Table 39). Table 39 - CR15: UART1 FCR Shadow Register D6 D5 D4 D3 D2 D1 RCVR TRIGGE R LSB Reserved DMA MODE SELECT XMIT FIFO RESE T RCVR FIFO RESE T
D7 CR 15 R RCVR TRIGGER MSB
D0 FIFO ENABL E
Defaul t N/A
7.3.22 CR16
CR161 can only be accessed in the configuration state and after the CSR has been initialized to 16H. CR16 shadows the bits in the write-only UART2 run-time FCR register (Table 40). D7 CR16 R RCVR TRIGGE R MSB Table 40 - CR16: UART2 FCR Shadow Register D6 D D4 D3 D2 D1 5 RCVR XMIT DMA RCVR FIFO FIFO Reserved MODE TRIGGER SELECT RESET RESET LSB D0 FIFO ENABLE Default N/A
7.3.23 CR17
(Reserved). The default value of this register after power up is 003H.
7.3.24 CR18 - CR1D
CR18 - CR1D registers are Reserved and Read Only . The default value of these registers after power up is 00H.
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7.3.25 CR1E
(Reserved). The default value of this register after power up is 80H.
7.3.26 CR1F
(Reserved). The default value of this register after power up is 00H.
7.3.27 CR20
(Reserved). The default value of this register after power up is 3CH.
7.3.28 CR21 - CR22
Registers CR21 - CR22 are Reserved. Reserved bits cannot be written and return 0 when read.
7.3.29 CR23
CR23 can only be accessed in the configuration state and after the CSR has been initialized to 23H. The default value of this register after power up is 00H (Table 41). CR23 is used to select the base address of the parallel port. If EPP is not enabled, the parallel port can be set to 192 locations on 4-byte boundaries from 100H - 3FCH; if EPP is enabled, the parallel port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H (Table 42). To disable the parallel port, set ADR9 and ADR8 to zero. Parallel Port Address Decoding: nCS = '0' and A10 = '0' are required to access the Parallel Port when in Compatible, Bi-directional, or EPP modes. A10 is active when in ECP mode. Table 41 - CR23: Parallel Port Base Address Register DB5 DB4 DB3 DB2 DB1 ADR7 ADR6 ADR5 ADR4 ADR3 Table 42 - Parallel Port Addressing Options EPP ENABLED ADDRESSING (LOW BITS) DECODE No A[1:0] = XXb Yes A[2:0] = XXXb
DB7 ADR9
DB6 ADR8
DB0 ADR2
7.3.30 CR24
CR24 can only be accessed in the configuration state and after the CSR has been initialized to 24H. The default value of this register after power up is 00H (Table 43). CR24 is used to select the base address of Serial Port 1 (UART1). The serial port can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 1, set ADR9 and ADR8 to zero. Set CR24.0 to 0 when writing the UART1 Base Address. Serial Port 1 Address Decoding: nCS = '0' and A10 = '0' are required to access UART1 registers. A[2:0] are decoded as XXXb. Table 43 - CR24: UART1 Base Address Register DB5 DB4 DB3 DB2 ADR7 ADR6 ADR5 ADR4
DB7 ADR9
DB6 ADR8
DB1 ADR3
DB0 0
7.3.31 CR25
CR25 can only be accessed in the configuration state and after the CSR has been initialized to 25H. The default value of this register after power up is 00H (Table 44). CR25 is used to select the base address of Serial Port 2 (UART2). Serial Port 2 can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 2, set ADR9 and ADR8 to zero. Set CR25.0 to 0 when writing the UART2 Base Address. Serial Port 2 Address Decoding: nCS = '0' and A10 = '0' are required to access UART2 registers. A[2:0] are decoded as XXXb.
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DB7 ADR9
DB6 ADR8
Table 44 - CR25: UART2 Base Address Register DB5 DB4 DB3 DB2 ADR7 ADR6 ADR5 ADR4
DB1 ADR3
DB0 0
7.3.32 CR26
CR26 can only be accessed in the Configuration State and after the CSR has been initialized to 26H. The default value of this register after power up is 00H (Table 45). CR26 is used to select the DMA for the Parallel Port (bits 0 3). Any unselected DMA Request output (DRQ) is in tristate. Table 45 - CR26: PP DMA Selection Register D3-D0 DMA SELECTED 0000 None 0001 DMA_A 0010 DMA_B 0011 DMA_C
7.3.33 CR27
CR27 can only be accessed in the configuration state and after the CSR has been initialized to 27H. The default value of this register after power up is 00H (Table 46). CR27 is used to select the Parallel Port (bits 3 - 0). Any unselected IRQ output (registers CR27 - CR29) is in tristate. Table 46 - CR27: PP IRQ Selection Register D3-D0 IRQ SELECTED 0000 None 0001 IRQ_A 0010 IRQ_B 0011 IRQ_C 0100 IRQ_D 0101 IRQ_E 0110 IRQ_F 0111 Reserved 1000 IRQ_H
7.3.34 CR28
CR28 can only be accessed in the configuration state and after the CSR has been initialized to 28H. The default value of this register after power up is 00H. CR28 is used to select the IRQ for Serial Port 1 (bits 7 - 4) and for Serial Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 46). Any unselected IRQ output (registers CR27 CR29) is in tristate. To properly share an IRQ between UART1 and UART2: 1. 2. Configure UART1 to use the desired IRQ pin. Set UART2 to 0FH i.e., set CR28.[3:0] = 1111b. This selects the share IRQ mechanism. Refer to Table 47, below. Table 47 - UART Interrupt Operation UART1 UART2 IRQ PINS UART1 OUT2 bit 0 1 1 0 0 1 UART1 IRQ Output State Z asserted de-asserted Z Z asserted UART2 OUT2 bit 0 0 0 1 1 1 UART2 IRQ Output State Z Z Z asserted de-asserted asserted Share IRQ No No No No No No UART1 Pin State Z 1 0 Z Z 1 UART2 Pin State Z Z Z 1 0 1
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UART1 UART2 IRQ PINS UART1 UART1 IRQ UART2 UART2 IRQ Share UART1 UART2 Output State OUT2 bit Output State IRQ OUT2 bit Pin State Pin State 1 asserted 1 de-asserted No 1 0 1 de-asserted 1 asserted No 0 1 1 de-asserted 1 de-asserted No 0 0 0 Z 0 Z Yes Z Z 1 asserted 0 Z Yes 1 Z 1 de-asserted 0 Z Yes 0 Z 0 Z 1 asserted Yes 1 Z 0 Z 1 de-asserted Yes 0 Z 1 asserted 1 asserted Yes 1 Z 1 asserted 1 de-asserted Yes 1 Z 1 de-asserted 1 asserted Yes 1 Z 1 de-asserted 1 de-asserted Yes 0 Z It is the responsibility of the software to ensure that two IRQ's are not set to the same IRQ number. Potential damage to chip may result. Note: Z = Don't Care.
7.3.35 CR29
CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H. The default value of this register after power up is 00H (Table 48). CR29 is used to select the IRQ mapping (bits 0 - 3) for the IRQIN pin. Refer to IRQ encoding for CR27 (Table 46). Any unselected IRQ output (registers CR27 - CR29) is in tristate. Table 48 - CR29 DESCRIPTION Selects the IRQ for IRQIN Not Writeable, Reads Return "0"
BIT NO. 0-3 4-7
NAME IRQIN RESERVED
7.3.36 CR2A
Register CR2A is reserved. The default value of this register after power up is 00H.
7.3.37 CR2B
CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH. The default value of this register after power up is 00H (Table 49). CR2B is used to set the SCE base address ADR[10:3]. The SCE base address can be set to 224 locations on 8-byte boundaries from 100H - 7F8H. To disable the SCE, set ADR10, ADR9 and ADR8 to zero. SCE Address Decoding: nCS = '0' required to access SCE registers. A[2:0] are decoded as XXXb. DB7 ADR10 DB6 ADR9 Table 49 - CR2B: SCE Base Address Register DB5 DB4 DB3 DB2 ADR8 ADR7 ADR6 ADR5 DB1 ADR4 DB0 ADR3
7.3.38 CR2C
CR2C can only be accessed in the configuration state and after the CSR has been initialized to 2CH. The default value of this register after power up is 00H (Table 50). Bits D[3:0] of this register are used to select the DMA for the SCE. Bits D[7:4] are Reserved. Reserved bits cannot be written and return 0 when read. Any unselected DMA Request output (DRQ) is in tristate.
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Table 50 - CR2C: SCE DMA Select Register D3-D0 DMA SELECTED 0000 None 0001 DMA_A 0010 DMA_B 0011 DMA_C
7.3.39 CR2D
CR2D can only be accessed in the configuration state and after the CSR has been initialized to 2DH. The default value of this register after power up is 03H. Table 51 - CR2D D4 D3 Reserved
D7 CR2D R/W
D6
D5
D2
D1
D0
DEFAULT 0x03
7.3.40 CR2E
CR2E can only be accessed in the configuration state and after the CSR has been initialized to 2EH. The default value of this register after power up is 00H (Table 52). Table 52 - CR2E D4 D3 Software Select A
D7 CR2E R/W
D6
D5
D2
D1
D0
DEFAUL T 0x00
7.3.41 CR2F
CR2F can only be accessed in the configuration state and after the CSR has been initialized to 2FH. The default value of this register after power up is 00H (Table 53). Table 53 - CR2F D4 D3 Software Select B
D7 CR2F R/W
D6
D5
D2
D1
D0
DEFAUL T 0x00
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8 8.1
OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS
Operating Temperature Range........................................................................................................................... 0oC to +70oC Storage Temperature Range ............................................................................................................................-55o to +150oC Lead Temperature Range (soldering, 10 seconds) ..................................................................................................... +325oC Positive Voltage on any pin, with respect to Ground ......................................................................................................+5.5V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V Maximum VCC .....................................................................................................................................................................+5V *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
8.2
DC ELECTRICAL CHARACTERISTICS
Table 54 - DC Electrical Characteristics PARAMETER I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage High Input Leakage Input Current PWRGD IIL IIH IOH -10 -10 75 +10 +10 150 A A A VIN = 0 VIN = Vcc VIN = 0 VILCK VIHCK 2.2 0.4 V V VILIS VIHIS VHYS 2.2 250 0.8 V V mV Schmitt Trigger Schmitt Trigger VILI VIHI 2.0 0.8 V V TTL Levels SYMBOL MIN TYP MAX UNITS COMMENTS
(TA = 0C - 70C, Vcc = +3.3 V 10%)
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PARAMETER IO12 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage O12PD Type Buffer Low Output Level High Output Level Output Leakage O6 Type Buffer Low Output Level High Output Level Output Leakage OD14 Type Buffer Low Output Level Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type Buffer Low Output Level High Output Level Output Leakage
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 12mA IOH = -6mA VIN = 0 to Vcc (Note 1)
+10
A
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 12mA IOH = -6mA VIN = 0 to Vcc (Note 1)
+10
A
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 12mA IOH = -6mA VIN = 0 to Vcc (Note 1)
+10
A
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 6mA IOH = -3mA VIN = 0 to Vcc (Note 1)
+10
A
VOL IOL -10
0.4 +10
V A
IOL = 14mA VIN = 0 to Vcc (Note 1)
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 14mA IOH = -14mA VIN = 0 to Vcc (Note 1)
+10
A
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 14mA IOH = -14mA VIN = 0 to Vcc (Note 1)
+10
A
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PARAMETER O4 Type Buffer Low Output Level High Output Level Output Leakage OD12 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby ChiProtect
(SLCT, PE, BUSY, nACK, nERROR)
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 4mA IOH = -2mA VIN = 0 to Vcc (Note 1)
+10
A
VOL IOL ICC ICSBY IIL -10 15
0.4 +10 20 100 10
V A mA A A
IOL = 12 mA VIN = 0 to Vcc (Note 1) All outputs open. Note 3 Chip in circuit: VCC = 0V VIN = 5.5V Max. Chip in circuit: VCC = 0V VIN = 5.5V Max.
Backdrive Protect
(nSLCTIN, nINIT, nAUTOFD, nSTROBE, PD[7:0])
IIL
10
A
Note 1: Output leakage is measured with the current pins in high impedance as defined by the PWRGD pin. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state defined by PWRGD. Note 3: Defined by the device configuration with the PWRGD input low. CAPACITANCE TA = 25C; fc = 1MHz; VCC = 3.3V Table 55 - Clock Pin Loading PARAMETER Clock Input Capacitance SYMBOL MIN CIN LIMITS TYP UNIT MAX 20 pF TEST CONDITION All pins except pin under test tied to AC ground
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
Table 56 - Capacitive Loading per Output Pin SIGNAL NAME TOTAL CAPACITANCE (pF) SD[0:7] 240 IOCHRDY 240 IRQs 120 DRQs 120 TXD 100 nRTS 100 nDTR 100 PD[7:0] 240 nSLCTIN 240 nINIT 240
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9 9.1
AC TIMING Host Timing
AX, AEN, nIOCS16 nIOR t3
t1 t6 t2
DATA (D0-D7) PD0-PD7, nERR, PE, SLCT, nACK, BUSY nIOR/nIOW
t4
t5
DATA VALID
t8
PINTR
t9
PINTR is the interrupt assigned to the Parallel Port
Parameter t1 t2 t3 t4 t5 t6 t8 t9 A0-A9, AEN, nIOCS16 Set Up to nIOR Low nIOR Width A0-A9, AEN, nIOCS16 Hold from nIOR High Data Access Time from nIOR Low Data to Float Delay from nIOR High Parallel Port Setup
min 40 150 10
typ
max
units ns ns ns
10 20
100 60
ns ns ns ns
nIOR or nIOW Inactive for Transfers to150 and from ECP FIFO nIOR Active to PINTR Inactive FIGURE 4 - MICROPROCESSOR READ TIMING
260
ns
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AX, AEN, nIOCS16 t2 nIOW t1 t4
t3
DATA (D0-D7)
t5
DATA VALID
PINTR
t7
PINTR is the interrupt assigned to the Parallel Port
Parameter t1 t2 t3 t4 t5 t7 A0-A9, AEN, nIOCS16 Set Up to nIOW Low nIOW Width A0-A9, AEN, nIOCS16 Hold from nIOW High Data Set Up Time to nIOW High Data Hold Time from nIOW High
min 40 150 10 40 10
typ
max
units ns ns ns ns ns
nIOW Inactive to PINTR Inactive FIGURE 5 - MICROPROCESSOR WRITE TIMING
260
ns
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t1 X1K nRESET t4 t2 t2
Parameter t1 t2 t1 t2 t4 Clock CycleTime for 14.318MHZ Clock High Time/Low Time for 14.318MHZ Clock Cycle Time for 32KHZ Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown) nRESET Low Time
min
typ 70 35 31.25 16.53
max 65
units ns ns us us ns us
5
1.5
The nRESET low time is dependent upon the processor clock. The nRESET must be active for a minimum of 24 x16MHz clock cycles.
FIGURE 6 - CLOCK TIMING
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9.2
Serial Port Timing
nIOW t1
nRTSx, nDTRx IRQx nCTSx, nDSRx, nDCDx
t5
t6 t2 IRQx nIOW t3 IRQx nIOR nRIx t4
Parameter t1 t2 t3 t4 t5 t6 nRTSx, nDTRx Delay from nIOW IRQx Active Delay from nCTSx, nDSRx, nDCDx IRQx Inactive Delay from nIOR (Leading Edge) IRQx Inactive Delay from nIOW (Trailing Edge) IRQx Inactive Delay from nIOW IRQx Active Delay from nRIx
min
typ
max 200 100 120 125
units ns ns ns ns ns ns
10
100 100
FIGURE 7 - SERIAL PORT TIMING
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9.3
Parallel Port Timing
PD0- PD7 t6 nIOW t1
nINIT, nSTROBE. nAUTOFD, SLCTIN
PINTR (SPP)
nACK t2
PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) t5 PINTR t2 t3
t4
t3
Parameter t1 t2 t3 t4 t5 t6 nINIT, nSTROBE, nAUTOFD Delay from nIOW Inactive PINTR Delay from nACK, nFAULT PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK nERROR Active to PINTR Active PD0-PD7 Delay from nIOW Active
min
typ
max 100 60 300 105 105 100
units ns ns ns ns ns ns
200
PINTR is the interrupt assigned to the Parallel Port
FIGURE 8 - PARALLEL PORT TIMING
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9.3.1
PARALLEL PORT EPP TIMING
t18 t9 t17 t8 t10 t13 nWRITE PD<7:0> t20 t1 t16 t3 t2 t5 t11 t12 t19
AX SD<7:0> nIOW IOCHRDY
nDATAST nADDRSTB
t14
t4
nWAIT
t6
t15
t7
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 NOTE: nIOW Asserted to PDATA Valid nWAIT Asserted to nWRITE Change nWRITE to Command Asserted nWAIT Deasserted to Command Deasserted nWAIT Asserted to PDATA Invalid Time Out Command Deasserted to nWAIT Asserted SDATA Valid to IOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted WAIT Deasserted to nIOCHRDY Deasserted IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted nWAIT Asserted to Command Asserted Command Asserted to nWAIT Deasserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to nWRITE Asserted
min 0 60 5 60 0 10 0 10 0 0 60 10 0 60 0 10 40 10 40 60
max 50 185 35 190 12
units ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns ns ns
Notes 1 1 1
24 160 70 210 10
1
1
185
1
WAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec.
FIGURE 9 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE
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t20 AX IOR t19 t13 SD<7:0> t8 t18 t10 t11 t12 t22
IOCHRDY
t9 t21 nWRITE t2 t25 PD<7:0> t28 t1 DATASTB ADDRSTB t15 nWAIT t7 t6 t14 t3
PData bus driven
t17
t5
by peripheral
t4
t16
Timing parameter table for the EPP Data or Address Read Cycle is found on next page.
FIGURE 10 - EPP 1.9 DATA OR ADDRESS READ CYCLE
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Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t25 t28 PDATA Hi-Z to Command Asserted nIOR Asserted to PDATA Hi-Z nWAIT Deasserted to Command Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid PDATA Hi-Z to nWAIT Deasserted PDATA Valid to nWAIT Deasserted nIOR Assertd to IOCHRDY Asserted nWRITE Deasserted to nIOR Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA Hi-Z (Hold Time) PDATA Valid to SDATA Valid nWAIT Asserted to Command Asserted Time Out nWAIT Deasserted to PDATA Driven nWAIT Deasserted to nWRITE Modified SDATA Valid to IOCHRDY Deasserted Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR Deasserted to nIOW or nIOR Asserted nWAIT Asserted to PDATA Hi-Z WRITE Deasserted to Command
min 0 0 60 0 0 0 0 0 0 60 0 0 0 0 10 60 60 0 40 10 0 40 60 1
max 30 50 180
units ns ns ns ns ns s ns ns ns ns ns
Notes
1
24 160
2 1
40 75 195 12 190 190 85 10 185 180
ns ns ns s ns ns ns ns ns ns ns ns ns
1 1,2 3
1
NOTES: 1. n WAIT is considered to have settled after it does not transition for a minimum of 50 ns. 2. When not executing a write cycle, EPP nWRITE is inactive high. 3. 85 is true only if t7 = 0.
FIGURE 11 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS
SMSC DS - SP37E760
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AX
t18
SD<7:0>
t9
nIOW
t17 t8
t6 t12 t19
IOCHRDY
t10 t20
t11
nWRITE
t13
t2
PD<7:0>
t1
t5
nDATAST nADDRSTB
t16 t3
t4
nWAIT
t21
Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t16 t17 t18 t19 t20 t21 nIOW Asserted to PDATA Valid Command Dessserted to nWRITE Change nWRITE to Command nIOW Deasserted to Command Deasserted Command Deasserted to PDATA Invalid Time Out SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted PDATA Valid to Command Asserted Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid nIOW Deasserted to nIOW or nIOR Asserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to nWAIT Deasserted
min 0 0 5 50 10 10 0 0 10 0 10 40 10 100 0
max 50 40 35 50 12
units ns ns ns ns ns s ns ns ns ns ns ns ns ns s ns ns ns
Notes
2
24 40 50 35
45
NOTES: 1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP W rite. 2. This number is only valid if WAIT is active when nIOW goes active. FIGURE 12 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE
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t20 AX t15 nIOR t19 t11 t22
t13 SD<7:0> t8 IOCHRDY t3 t10
t12
nWRITE t5 PD<7:0> t23 nDATASTB nADDRSTB t21 nWAIT t2 t4
Parameter t2 t3 t4 t5 t8 t10 t11 t12 t13 t15 t19 t20 t21 t22 t23 nIOR Deasserted to Command Deasserted nWAIT Asserted to IOCHRDY Deasserted Command Deasserted to PDATA Hi-Z Command Asserted to PDATA Valid nIOR Asserted to IOCHRDY Asserted nWAIT Deasserted to nIOCHRDY Deasserted nIOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA High-Z (Hold Time) PData Valid to SDATA Valid Time Out Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid Command Deasserted to nWAIT Deasserted nIOR Deasserted to nIOW or nIOR Asserted nIOR Asserted to Command Asserted
min 0 0 0
max 50 40
units ns ns ns ns ns ns ns ns ns s ns ns ns ns ns
Notes
24 50 0 0 10 40 10 0 40 40 40 12
55
NOTE: 1. nWRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read. FIGURE 13 - EPP 1.7 DATA OR ADDRESS READ CYCLE
9.3.2
PARALLEL PORT ECP TIMING
9.3.2.1 Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does not examine nAck and begins the next transfer based on Busy. Refer to FIGURE 14. 9.3.2.2 ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. 9.3.2.3 Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low.
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9.3.2.4 Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriph Request. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriph Request (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in FIGURE 15. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). 9.3.2.5 Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. 9.3.2.6 Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nAutoFd) low. The peripheral then sets PeriphClk (nAck) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready it to accept a byte it sets. HostAck (nAutoFd) high to acknowledge the handshake. The peripheral then sets PeriphClk (nAck) high. After the host has accepted the data it sets HostAck (nAutoFd) low, completing the transfer. This sequence is shown in FIGURE 16. 9.3.2.7 Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driverchange is specified in the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July. 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs.
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Rev. 04/13/2001
t3 PDATA t1 t2 t5
nSTROBE
t4 BUSY
Paramet t1 t2 t3 t4 t5 t6 DATA Valid to nSTROBE nSTROBE Active Pulse DATA Hold from nSTROBE nSTROBE Active to BUSY BUSY Inactive to nSTROBE BUSY Inactive to PDATE
min 600 600 450
max
units ns ns ns ns ns ns
Note
1
500 680 80
1
NOTE 1. The data is held until BUSY goes inactive or for time t3, whichever is applies if another data transfer is pending. If no other data transfer is is held FIGURE 14 - PARALLEL PORT FIFO TIMING
SMSC DS - SP37E760
Rev. 04/13/2001
t3 nAUTOFD t4 PDATA<7:0> t2 t1 t7 nSTROBE t6 BUSY t5 t6 t8
Parameter t1 t2 t3 t4 t5 t6 t7 t8 nAUTOFD Valid to nSTROBE Asserted PDATA Valid to nSTROBE Asserted BUSY Deasserted to nAUTOFD Changed nBUSY Deasserted to PDATA Changed nSTROBE Asserted to BUSY Asserted nSTROBE Deasserted to Busy Deasserted nBUSY Deasserted to nSTROBE Asserted nBUSY Asserted to nSTROBE Deasserted
min 0 0 80 80 0 0 80 80
max 60 60 180 180
units ns ns ns ns ns ns ns ns
Notes
1,2 1,2
200 180
1,2 2
NOTES: 1. Maximum value only applies if there is data in the FIFO waiting to be written out. 2. BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. FIGURE 15 - ECP PARALLEL PORT FORWARD TIMING
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Rev. 04/13/2001
t2 PDATA<7:0> t1 t5 nACK t4 nAUTOFD t3 t4 t6
Parameter t1 t2 t3 t4 t5 t6 PDATA Valid to nACK Asserted nAUTOFD Deasserted to PDATA Changed nACK Asserted to nAUTOFD Deasserted nACK Deasserted to nAUTOFD Asserted nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted
min 0 0 80 80 0 0
max
units ns ns
Notes
200 200
ns ns ns ns
1,2 2
NOTES: 1. Maximum value only applies if there is room in the FIFO and a terminal count has not been received. ECP can stall by keeping nAUTOFD low. 2. nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
FIGURE 16 - ECP PARALLEL PORT REVERSE TIMING
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Rev. 04/13/2001
10 PACKAGE OUTLINES
D D 1
E
E1
e
W
A H CD IM A A1 A2 D D1 E E1 H L L1 e 0 W TD (1 ) TE(1 ) TD (2 ) TE(2 ) 0 .1 0
A2
TD / TE
0 A1 L L 1 MA X 3.15 0.45 2.87 24 .1 5 20 .1 18 .1 5 14 .1 0 .2 0.95 2 .6 0 .6 5 BSC 0 .2 2 1.8 1 5.8 22 .2 1 16 .2 7 12 .4 22 .2 16 .2 22 .7 6 16 .8 2 M IN .11 0 .00 4 .10 1 .92 1 .78 3 .68 5 .54 7 .00 4 .02 6 .07 1 MA X .1 24 .0 18 .1 13 .9 51 .7 91 .7 15 .5 55 .0 08 N otes : 1 ) C op la na rity is 0 .1 00 mm (.00 4") max imu m. 2 ) To le ran c e o n th e po s ition o f th e le ad s is 0 .2 00 mm (.00 8") max imu m. 3 ) Pa c k ag e bo dy d ime ns io ns D 1 a nd E1 do n ot inc lu de the mo ld p rotrus io n. Max imu m mo ld pro tru s ion is 0.25 mm (.01 0"). 4) D imen s ion s TD an d TE a re imp ortan t fo r tes ting by ro bo tic ha nd le r. On ly a bo v e c omb in atio ns o f (1) or (2) are a c c ep ta ble. 5) C o ntrolling d ime ns io n: millimeter. D ime ns io ns in inc he s fo r re fe ren c e o nly an d no t ne c e s s arily
M IN 2 .8 0 0 .1 2 .5 7 2 3.4 1 9.9 1 7.4 1 3.9 0 .1 0 .6 5 1 .8
.0 37 .1 02 .02 56 BSC 0 12 .01 6 .87 4 .63 8 .89 6 .66 2
ac c u rate.
.00 8 .85 8 .62 2 .87 4 .64 1
FIGURE 17 - 100 PIN QFP
SMSC DS - SP37E760
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Rev. 04/13/2001
3 3
D D1
e E E1 5 W
D1/4
2
E1/4
DETAIL "A" R1 R2 0
A H 1 0.10 -CA1
A2 SEE DETAIL "A"
4
L L1
DIM A A1 A2 D D1 E E1 H L L1 e 0 W R1 R2
MIN 0.05 1.35 15.75 13.90 15.75 13.90 0.45
NOM
MAX 1.6 1.45 16.25 14.10 16.25 14.10 0.20 0.75
1.40 16.00 14.00 16.00 14.00 0.60 1.00 0.50 BSC 0.25 0.20 0.20
0
8
Notes: 1 Coplanarity is 0.100mm maximum. 2 Tolerance on the position of the leads is 0.13mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25mm per side. 4 Dimension for foot length L are measured at the gauge plane 0.25mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Controlling dimension: millimeter
FIGURE 18 - 100 PIN TQFP
SMSC DS - SP37E760
Page 77
Rev. 04/13/2001
11 SP37E760 REVISIONS
PAGE(S) 1 SECTION/FIGURE/ENTRY Title CORRECTION 3.3V Super I/O Controller for Embedded Applications changed to: 3.3V I/O Controller for Embedded Applications DATE REVISED 04/13/01
SMSC DS - SP37E760
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Rev. 04/13/2001

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